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CXA2543R decoder/driver/timing generator for color lcd panels description the CXA2543R is an ic designed exclusively to drive the color lcd panel dcx501bk and lcx018ak. this ic greatly reduces the number of circuits and parts required to drive lcd panels by incorporating rgb decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip. this chip has a built-in serial interface circuit and electronic attenuators which allow various mode settings and adjustments to be performed through direct control from an external microcomputer, etc. features color lcd panel dcx501bk and lcx018ak driver supports ntsc and pal signals supports 16:9 wide display supports composite inputs, y/c inputs and y/color difference inputs serial interface circuit electronic attenuators (d/a converter) bpf, trap and delay line sharpness function 2-point g correction circuit r, g, b signal delay time adjustment circuit polarity inversion circuit (line inverted mode) supports external rgb input supports ac drive for lcd panel during no signal applications compact lcd monitors lcd viewfinders compact liquid crystal projectors, etc. structure bipolar cmos ic absolute maximum ratings (ta = 25?) supply voltage v cc 1 ?gnd1 6 v v cc 2 ?gnd2 14 v v cc 3 ?gnd3 14 v v dd 1 ?v ss 1 4.5 v v dd 1 ?v ss 2 4.5 v analog input pin voltage vina ?.3 to v cc v digital input pin voltage vind ?.3 to v dd 1 + 0.3 v operating temperature topr ?5 to +75 ? storage temperature tstg ?0 to +125 ? allowable power dissipation * 1 p d (ta 75?) 350 mw operating conditions supply voltage v cc 1 ?gnd1 4.25 to 5.25 v v cc 2 ?gnd2 11.0 to 13.5 v v cc 3 ?gnd3 11.0 to 13.5 v v dd 1 ?v ss 1 2.7 to 3.6 v v dd 1 ?v ss 2 2.7 to 3.6 v * 1 with substrate size: 30 30 1.6mm material: glass fabric base epoxy ?1 e98403-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 64 pin lqfp (plastic)
? 2 CXA2543R block diagram p o l s w s u b - b r i g h t g a m m a d e m o d l p f c o n t r a s t e x t s w b r i g h t s / h i n t / e x t v x o h u e p s k i l l e r f i l t a d j c o l o r c o n t b p f p i c c o n t d l 1 t r a p c l a m p a c c a m p h . f i l t e r b u f r e g . r g b + 1 2 v + 1 2 v g n d 1 v s s 1 + 4 . 5 v b u f b u f p a l s w e x t c o l o r & b a l a n c e h u e h u e c o l o r c o n t r a s t r - b r t b - b r t g - 1 g - 2 s e r i a l b u s i / f v s s 2 v g a t e v t s t v p a l v w i n w i d e p a l s w d / a h c n t h - p u l s e h a f c p l l - c o u n t e r & d e c o d e r h g a t e h - s k e w d e t p d c l p b g p s b l k v s e p + 3 v m a t r i x b u f b u f p o l s w p s i g - b r i g h t p s i g - b r t a p c a c c d e t h d g n d 3 g n d 2 s y n c s e p f r p c o l o r p a l i d c l a m p v d v s s 2 e n x e n v c k 1 v c k 2 v s t x v s t f l d i n h d p c g x p c g h c k 1 h c k 2 h s t x h s t 4 6 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 v d d 1 c k o c k i v s s 1 r p d t e s t 2 e x t b e x t g e x t r s . s e p i n h . f i l o u t s y n c i n g n d 1 t r a p t e s t 1 v d i n v c c 1 s i g . c e n t e r b - y i n r - y i n b l k l i m a p c v x o o u t v x o i n v r e g c i n t e s t 3 y i n p i c p w r s t f 0 a d j c o u t s c l k d a t a l o a d r g t f b p s i g g n d 3 p s i g v c c 3 b o u t f b b g o u t f b g r o u t f b r v c c 2 g n d 2 b r i g h t
? 3 CXA2543R pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 trap gnd1 sync in h.fil out s.sep in ext r ext g ext b vd in test1 test2 rpd v ss 1 cki cko v dd 1 xhst hst hck2 hck1 xpcg pcg hd fld in xvst vst vck2 vck1 xen en v ss 2 vd symbol h h i o i i i i i o i o o o o o o o o i o o o o o o o external trap connection analog (4.5v) gnd video input for sync separation video output for sync input sync separation circuit input external digital input r external digital input g external digital input b external vertical sync input test (leave this pin open.) test (leave this pin open.) phase comparator output digital (3v) gnd for oscillation cell oscillation cell input oscillation cell output digital 3v power supply xh start pulse output (hst reversed polarity) h start pulse output h clock pulse 2 output h clock pulse 1 output xpcg pulse output (pcg reversed polarity) pcg pulse output hd pulse output field identification input xv start pulse output (vst reversed polarity) v start pulse output v clock pulse 2 output v clock pulse 1 output xen pulse output (en reversed polarity) en pulse output digital (3v) gnd vd pulse output i/o description input pin for open status (h: pull up)
? 4 CXA2543R 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 h h h h sclk data load rgt fb psig gnd3 psig v cc 3 b out fb b gnd2 g out fb g r out fb r v cc 2 v cc 1 sig.center b-y in r-y in c out blk lim apc vxo out vxo in v reg c in test3 y in pic f0 adj pwrst i i i i o o o o o o o o i i i o i o o i o i i i i o serial interface clock input serial interface data input serial interface load input switches between normal scan (h) and reverse scan (l) psig signal dc voltage feedback circuit capacitor connection analog (12v) gnd for psig psig output analog 12v power supply for psig b signal output b signal dc voltage feedback circuit capacitor connection analog (12v) gnd g signal output g signal dc voltage feedback circuit capacitor connection r signal output r signal dc voltage feedback circuit capacitor connection analog 12v power supply analog 4.5v power supply r, g, b and psig output dc voltage adjustment b-y demodulator input (or b-y color difference signal input) r-y demodulator input (or r-y color difference signal input) chroma signal output black peak limiter level adjustment apc detective filter connection vxo output vxo input constant voltage capacitor connection chroma signal input test (connect to gnd.) y signal input y signal frequency response adjustment internal filter adjusting resistor connection system reset (h: pull up) pin no. symbol i/o description input pin for open status
? 5 CXA2543R analog block pin description pin no. symbol pin voltage equivalent circuit description 1 trap 2 gnd1 0v analog (4.5v) gnd. v c c 1 g n d 1 1 3 0 a 1 k 3 0 0 7 0 a 1 external trap connection. connect the trap between this pin and gnd to remove the chroma component. leave this pin open when using y/c and y/color difference input. 3 sync in 1.5v sync input. normally inputs the y signal. the standard signal input level is 0.5vp-p (100% white level from the sync tip). v d d 1 g n d 1 1 k 3 0 a 3 2 . 1 v 1 k 4 h.fil out 0.8v outputs the video signal for input to the sync separation circuit. v d d 1 g n d 1 2 0 k 2 0 k 4 5 s.sep in 2.1v sync separation circuit input. input the h.fil out (4pin) signal. v d d 1 g n d 1 1 7 k 1 . 8 v 1 0 a 2 . 8 v 5
? 6 CXA2543R 6 ext-r 7 ext-g 8 ext-b 42 fb b 37 fb psig 45 fb g 47 fb gr 41 b out 44 g out 46 r out external digital signal inputs. there are two threshold values: vth1 (= 1.0v) and vth2 (= 2.0v). when one of the rgb signals exceeds vth1, all of the rgb outputs go to black level; when an input exceeds vth2, only the corresponding output goes to white level. 6 8 3 0 0 v c c 1 g n d 1 3 0 a 5 0 k 2 . 7 v 7 smoothing capacitor connection for the feedback circuit of r, g, b and psig output dc level control. use a low-leakage capacitor because of high impedance. 1 k v c c 1 g n d 2 4 2 3 7 4 5 4 7 v cc 2 2 rgb signal outputs. 4 6 v c c 2 g n d 2 4 0 a 2 0 2 0 4 4 4 1 2.0v 38 gnd3 0v analog (12v) gnd for the psig circuit. psig signal outputs. v c c 3 g n d 3 1 0 3 9 39 psig v cc 2 2 40 v cc 3 12v 12v power supply for the psig circuit. 43 gnd2 0v analog (12v) gnd. pin no. symbol pin voltage equivalent circuit description
? 7 CXA2543R 51 b-y in 52 r-y in color difference demodulation circuit inputs. color difference signal is input when using y/color difference input. at this time, the standard signal input level is 0.3vp-p and the clamp level is approximately 2.8v. pin 53 signal is input in other modes (except d-pal * ). at this time, the dc level is approximately 1.6v. 5 0 0 g n d 1 1 0 k 3 0 a 5 0 a v c c 1 5 0 0 5 2 5 1 50 sig. center 6.0v rgb output dc voltage control. when used with a v cc 2 and v cc 3 of 12v or more, apply 6v from an external source. v c c 2 g n d 2 1 5 0 k 3 0 0 1 5 0 k 5 0 53 c out 1.6v color adjusted chroma signal output. the burst level is 180mvp-p (typ.). (540mvp-p during d-pal.) leave this pin open when using y/color difference input. v c c 1 g n d 1 3 5 0 a 5 3 54 blk lim sets the rgb output amplitude (black-black) clip level and the blanking black level for during wide display. v c c 1 g n d 1 5 0 k 5 4 5 0 k * d-pal is a demodulation method that uses an external delay line during demodulation; s-pal is a demodulation method that internally processes chroma demodulation. 48 v cc 2 12v 49 v cc 1 4.5v 12v power supply. 4.5v power supply. pin no. symbol pin voltage equivalent circuit description
? 8 CXA2543R 56 vxo out 2.9v vxo output. leave this pin open when using y/color difference input. v c c 1 g n d 1 4 0 0 a 5 6 57 vxo in 3.2v vxo input. leave this pin open when using y/color difference input. v c c 1 g n d 1 2 . 4 k 5 0 0 3 . 2 v 5 7 58 v reg 3.6v smoothing capacitor connection for the internally generated constant voltage source circuit. connect a capacitor of 1 f or more. v c c 1 g n d 1 6 0 k 3 0 k 5 8 59 c in video signal input when using composite input. chroma signal input when using y/c signal input. leave this pin open when using y/color difference input. v c c 1 g n d 1 2 0 k 5 0 0 3 0 a 5 9 1 5 p 55 apc 2.7v apc detective filter connection. leave this pin open when using y/color difference input. v c c 1 g n d 1 1 k 5 5 pin no. symbol pin voltage equivalent circuit description
? 9 CXA2543R 61 y in y signal input. the standard signal input level is 0.5vp-p (100% white level from the sync tip). input at low impedance (75 or less). v c c 1 g n d 1 7 0 a 1 k 6 1 63 f0 adj 3.0v connect resistance of 15k between this pin and gnd1 to adjust the internal filters using the outflow current value. connect to +4.5v power supply when using y/c or y/color difference input. v c c 1 g n d 1 1 5 a 1 k 6 3 64 pwrst tg block system reset pin. the system is reset when this pin is connected to gnd. connect a capacitor between this pin and gnd. 1 k v d d 1 g n d 1 2 a 6 4 62 pic adjusts frequency response of luminance signal. increasing the voltage emphasizes contours. v c c 1 g n d 1 3 0 k 1 0 k 5 0 a 2 0 k 5 0 a 6 2 b i a s 3.1v pin no. symbol pin voltage equivalent circuit description
? 10 CXA2543R setting conditions for measuring electrical characteristics use the electrical characteristics measurement circuit on page 30 when measuring electrical characteristics. also, the tg (timing generator) block must be initialized by performing settings 1 and 2 below. setting 1. system reset after turning on the power, set sw64 to on and start up v64 from gnd in order to activate the tg block system reset. (see fig. 1-1.) the serial bus will be set to default values. setting 2. horizontal afc adjustment input sig5 (vl = 0mv) to (a) and adjust v14 so that wl and wh of the tp12 output waveform are the same. (see fig. 1-2.) note) when measuring a band of 2mhz or more for y signal frequency response or sharpness response among the items being measured, the measurement must be made with sample-and-hold timing (serial bus) set to through (sample-and- hold not performed). v d d v 6 4 ( p w r s t ) t r > 1 0 s t r s i g 5 t p 1 2 w l = w h w l w h w s fig. 1-1. system reset fig. 1-2. horizontal afc adjustment
? 11 CXA2543R electrical characteristics ?dc characteristics unless otherwise specified, settings 1 and 2 and the following setting conditions are required. v cc 1 = 4.5v, v cc 2 = 12.0v, v cc 3 = 12.0v, gnd1 = gnd2 = gnd3 = 0v, v dd 1 = 3.0v, v ss 1 = v ss 2 = 0v, ta = 25 c sw54, sw62, sw64 = on sw6, sw7, sw8, sw59 = a sw51, sw52 = b v54 = 0v, v62 = 2.2v set the serial bus registers to the "serial bus register initial settings". unspecified the serial bus registers should be set to default settings. input sig4 to (a) and sig2 (0db) to (b). measure the i cc 1 current value. comp input mode input sig4 to (a) and sig2 (0db) to (b). measure the i cc 1 current value. y/c input mode input sig4 to (a), (d) and (e). measure the i cc 1 current value. sw51, sw52 = a, sw59 = b y/color difference input mode input sig4 to (a) and sig2 (0db) to (b). measure the i cc 2 current value. psig load capacity clp = 0pf input sig4 to (a) and sig2 (0db) to (b). adjust psig-brt of the serial bus and measure the i cc 2 current value when tp39 output is set to 5vp-p. psig load capacity clp = 10000pf input sig4 to (a) and sig2 (0db) to (b). measure the i dd current value. dcx501 and lcx018 (4:3) mode input sig4 to (a) and sig2 (0db) to (b). measure the i dd current value. lcx018 (16:9) mode 23 21 17 6 6 6 7.5 30 28 23 8 8.3 8 10 37 35 29 10 10.5 10 12.5 ma ma ma ma ma ma ma i cc 11 i cc 12 i cc 13 i cc 2a i cc 2b i dd 1 i dd 2 item power supply characteristics current consumption v cc 1 current consumption v cc 2, 3 current consumption v dd symbol conditions min. typ. max. unit
? 12 CXA2543R digital block input pin * 1 0.3v dd v vil digital block i/o characteristics low level input voltage high level input voltage input current cki pin low input current cki pin high input current high level output voltage output pins except cko and rpd low level output voltage output pins except cko and rpd high level output voltage cko pin low level output voltage cko pin high level output voltage rpd pin low level output voltage rpd pin output off leak current rpd pin digital block input pin * 1 0.7v dd v vih input pin with pull-up resistor * 2 vin = v ss 2 ?45 ?0 ?4 a ii1 vin = v ss ?0 a ii2 vin = v dd 1 10 a ii3 ioh = ?ma * 3 2.8 v voh1 iol = 1ma * 3 0.3 v vol1 ioh = ?ma 0.5v dd v voh2 iol = 3ma 0.5v dd v vol2 * 1 digital block input pins: sclk, data, load, vdin, rgt, fldin, cki * 2 input pins with pull-up resistors: sclk, data, load, vdin, rgt, fldin * 3 output pins except cko and rpd: xhst, hst, hck1, hck2, xpcg, pcg, hd, xvst, vst, vck1, vck2, xen, en, vd ioh = ?.5ma v dd ? 1.2 v voh3 iol = 0.7ma 1.0 v vol3 high impedance status vout = v ss or vout = v dd 1 ?0 40 a ioff item symbol conditions min. typ. max. unit
? 13 CXA2543R electrical characteristics ?ac characteristics unless otherwise specified, settings 1 and 2 and the following setting conditions are required. v cc 1 = 4.5v, v cc 2 = 12.0v, v cc 3 = 12.0v, gnd1 = gnd2 = gnd3 = 0v, v dd 1 = 3.0v, v ss 1 = v ss 2 = 0v, ta = 25 c sw54, sw62, sw64 = on sw6, sw7, sw8 = a sw51, sw52, sw59 = b v54 = 0v, v62 = 2.2v set the serial bus registers to the "serial bus register initial values". unspecified serial bus registers should be set to default settings. unless otherwise specified, measure the non-inverted outputs for tp41, tp44 and tp46. input sig2 (0db) to (a). using a spectrum analyzer, measure the input and the 3.58mhz or 4.43mhz component of tp44, and obtain crleky = 150mv 1 0 ? clk/20 using their difference ? clk. 19 13 ? 5.0 2.5 3.0 5.0 22 17 ? 25 21 ? db db db mhz mhz mhz mhz gv gcnttp gcntmn fcyyc fcycmn fcycmp y signal block video maximum gain contrast characteristics typ contrast characteristics min y signal frequency response 1 y signal frequency response 2 10 14 ? 0 6 9 ? ? db db db db gshp1x fcl gshp1n gshp2x gshp2n picture quality adjustment variable amount 1 (y/c input) picture quality adjustment variable amount 2 (composite input) crleky 30 mv carrier leak (residual carrier) y/c input composite input (ntsc) composite input (pal) tdyyc tdycmn tdycmp 250 570 570 350 670 670 450 770 770 ns ns ns y signal i/o delay time y/c input composite input (ntsc) composite input (pal) input sig9 (vl = 150mv) to (a). measure the delay time from the 2t pulse peak of the input signal to the peak of the non-inverted output at tp44. input sig4 to (a) and measure the ratio between the output amplitude (white-black) and input amplitude at tp44. input sig4 to (a) and measure the ratio between the output amplitude (white-black) and input amplitude at tp44. input sig4 to (a) and measure the ratio between the output amplitude (white-black) and input amplitude at tp44. assume the output amplitude at tp44 when sig7 (0db, no burst, 100khz) is input to (a) as 0db. vary the frequency of the input signal to obtain the frequency with an output amplitude of ?db. v62 = 1.5v assume the output amplitude at tp44 when sig7 (0db, no burst, 100khz) is input to (a) as 0db. vary the frequency of the input signal to obtain the frequency with an output amplitude of ?db. v62 = 1.5v, load 500pf assume the output amplitude at tp44 when sig7 (100khz) is input to (a) as 0db. set sig7 to 2.5mhz and measure gshp1x and gshp1n as the amounts by which the output amplitude at tp44 changes when v62 = 4v and 0v, respectively. assume the output amplitude at tp44 when sig7 (100khz) is input to (a) as 0db. set sig7 to 2.0mhz and measure gshp2x and gshp2n as the amounts by which the output amplitude at tp44 changes when v62 = 4v and 0v, respectively. item symbol conditions min. typ. max. unit
? 14 CXA2543R input sig5 (vl = 150mv) to (a) and sig2 (level variable, 3.58mhz burst/chroma phase = 180 , or 4.43mhz burst/chroma phase = 135 ) to (b), and measure the output amplitude at tp44. gradually reduce the sig3 amplitude level and measure the level at which the killer operation is activated. sw59 = a ? 0 3 db ? 0 3 db ? ? 2 db ? 500 hz 500 hz 4 6 db ?5 ?5 db ?7 ?1 db ?4 ?8 db ? 2 db acc1 acc2 fapcn fapcp gcolmx gcolmn ackn ackp chroma signal block acc amplitude characteristics 1 acc amplitude characteristics 2 apc pull-in range color adjustment characteristics max color adjustment characteristics min ?0 ?0 deg 30 60 deg huemx huemn hue adjustment range max hue adjustment range min killer operation input level ntsc pal ntsc pal ntsc pal ntsc pal input sig5 (vl = 150mv) to (a) and sig2 (0db/+6db/?0db, 3.58mhz burst/chroma phase = 180 , or 4.43mhz burst/chroma phase = 135 ) to (b). measure the output amplitude at tp53, assuming the output corresponding to 0db, +6db and ?0db as v0, v1 and v2, respectively. acc1 = 20 log (v1/v0) acc2 = 20 log (v2/v0) sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, 3.58mhz burst/chroma phase = 180 , or 4.43mhz burst/chroma phase = 135 ) to (b). changing the sig2 burst frequency, measure the frequency f1 at which the tp44 output appears (the killer mode is canceled). ntsc: fapcn = f1 ?3579545hz pal: fapcp = f1 ?4433619hz sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, 3.58mhz burst/chroma phase = 180 ) to (b). assume the chroma output amplitude when serial bus register color = 80h, 0ffh and 0h as v0, v1 and v2, respectively. gcolmx = 20 log (v1/v0) gcolmn = 20 log (v2/v0) sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, burst/chroma phase variable) to (b). assume the phase at which the output amplitude at tp44 reaches a minimum when serial bus register hue = 80h, 0ffh and 0h as q 0, q 1 and q 2, respectively. huemx = q 1 ? q 0 huemn = q 2 ? q 0 sw59 = a item symbol conditions min. typ. max. unit
? 15 CXA2543R demodulation output amplitude ratio (ntsc) demodulation output amplitude ratio (pal) demodulation output phase difference (pal) color difference balance q rbn vgbn vrbn q gbn vrbp vgbp 99 0.25 0.53 230 109 0.32 0.63 242 119 0.39 0.73 254 deg 0.33 0.65 0.40 0.75 0.47 0.85 deg q rbp q gbp 80 232 90 244 100 256 deg deg gexcmx 4 6 db gexcmn color difference input color adjustment characteristics max color difference input color adjustment characteristics min color difference input balance adjustment r color difference input balance adjustment b ?0 ?5 db vexcbl 0.8 1.0 1.2 gexrmx 2 3 db gexrmn ? ? db gexbmx ? ? db gexbmn 2 3 db input sig5 (vl = 150mv) to (a) and sig2 (0db, 3.58mhz) to (b) and change the chroma phase. assume the maximum amplitude at tp41 as vb, the maximum amplitude at tp44 as vg, and the maximum amplitude at tp46 as vr. vrbn = vr/vb, vgbn = vg/vb sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, 3.58mhz) to (b) and change the chroma phase. assume the phase at which the amplitude at tp41, tp44 and tp46 reaches a maximum as q b, q g and q r, respectively. q rbn = q r ? q b, q gbn = q g ? q b sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, 4.43mhz) to (b) and change the chroma phase. assume the maximum amplitude at tp41 as vb, the maximum amplitude at tp44 as vg, and the maximum amplitude at tp46 as vr. vrbp = vr/vb, vgbp = vg/vb sw59 = a input sig5 (vl = 150mv) to (a) and sig2 (0db, 4.43mhz) to (b) and change the chroma phase. assume the phase at which the amplitude at tp41, tp44 and tp46 reaches a maximum as q b, q g and q r, respectively. q rbp = q r ? q b, q gbp = q g ? q b sw59 = a input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (d). assume the output amplitude at tp41 (100khz) when serial bus register color = 80h as vc0, when color = 0h as vc2, and when sig1 is set to -10db and color = 0ffh as vc1. gexcmx = 20 log (vc1/vc0) + 10 gexcmn = 20 log (vc2/vc0) sw51, sw52 = a input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (d) and (e). assume the output amplitude at tp41 (100khz) as vb and the output amplitude at tp46 (100khz) as vr. vexcbl = vr/vb sw51, sw52 = a input sig5 (vl = 150mv) to (a) and sig1 (?db, 100khz, no burst) to (d) and (e). assume the output amplitude at tp46 (100khz) and tp41 (100khz) when serial bus register hue = 80h as vr0 and vb0, respectively, when hue = 0ffh as vr1 and vb1, respectively, and when hue = 0h as vr2 and vb2, respectively. gexrmx = 20 log (vr1/vr0) gexrmn = 20 log (vr2/vr0) gexbmx = 20 log (vb1/vb0) gexbmn = 20 log (vb2/vb0) sw51, sw52 = a item symbol conditions min. typ. max. unit demodulation output phase difference (ntsc)
? 16 CXA2543R vexgbn 0.22 0.25 0.28 0.47 0.53 0.58 vexgrn 5.85 9.0 9.0 6.00 0 6.15 100 5.2 4.0 v mv vp-p vp-p vp-p vp-p g-y matrix characteristics (ntsc) input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (d). assume the output amplitude at tp41 (100khz) as vexb and the output amplitude at tp44 (100khz) as vexbg. vexgbn = vexbg/vexb sw51, sw52 = a input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (e). assume the output amplitude at tp46 (100khz) as vexr and the output amplitude at tp44 (100khz) as vexrg. vexgrn = vexrg/vexr sw51, sw52 = a vexgbp 0.16 0.19 0.22 0.48 0.53 0.58 vexgrp g-y matrix characteristics (pal) input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (d). assume the output amplitude at tp41 (100khz) as vexb and the output amplitude at tp44 (100khz) as vexbg. vexgbp = vexbg/vexb sw51, sw52 = a input sig5 (vl = 150mv) to (a) and sig1 (0db, 100khz, no burst) to (e). assume the output amplitude at tp46 (100khz) as vexr and the output amplitude at tp44 (100khz) as vexrg. vexgrp = vexrg/vexr sw51, sw52 = a vout ? vout vlimmx vlimmn brtmx brtmn input sig5 (vl = 0mv) to (a). adjust serial bus register bright so that the output (black-black) at tp44 is 9vp-p and measure the dc voltage at tp39, tp41, tp44 and tp46. input sig5 (vl = 0mv) to (a). adjust serial bus register bright so that the output (black-black) at tp44 is 9vp-p, measure the dc voltage at tp39, tp41, tp44 and tp46, and obtain the maximum difference between each of these values. input sig3 to (a). vary v54 and measure the maximum value vlimmx and minimum value vlimmn of the voltage range (black-black) over which the black limiter operates for the tp39, tp41, tp44 and tp46 outputs. assume the value whenv54 = 0v as vlimmx, and when v54 = 4.5v as vlimmn. input sig5 (vl = 0mv) to (a) and measure the output (black-black) at tp41, tp44 and tp46 when serial bus register bright = 0h. input sig5 (vl = 0mv) to (a) and measure the output (black-black) at tp41, tp44 and tp46 when serial bus register bright = 0ffh. rgb signal output block rgb signal and psig output dc voltage rgb signal and psig output dc voltage difference rgb and psig output limiter operation voltage amount of change in brightness item symbol conditions min. typ. max. unit
? 17 CXA2543R 1.5 vp-p 9.0 vp-p 1.5 2.0 v psigmx psigmn input sig5 (vl = 0mv) to (a) and measure the output (black-black) at tp39 when serial bus register psig-brt = 0h. input sig5 (vl = 0mv) to (a) and measure the output (black-black) at tp39 when serial bus register psig-brt = 0ffh. amount of change in psig sbbrt input sig5 (vl = 0mv) to (a) and measure the difference between the outputs (black-black) at tp41 and tp46 and the output (black-black) at tp44 when serial bus registers r-brt = b-brt = 0h and when r-brt = b-brt = 0ffh. amount of change in sub-brightness ?.5 0 0.5 db ? grgb input sig4 to (a) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white-black) at tp41, tp44 and tp46. difference in gain between rgb output signals ?.5 0 0.5 db ? ginv input sig4 to (a) and obtain the level difference between the non-inverted output amplitudes (white-black) and the inverted output amplitudes at tp41, tp44 and tp46. difference in rgb output inverted/non- inverted gain 300 mv ? vbl input sig4 to (a) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at tp41, tp44 and tp46. input sig8 to (a). adjust the non-inverted output black level at tp44 to 6.0 - 4.5v with serial bus register bright and the non-inverted output amplitude (white-black) at tp44 to 3.5v with serial bus register contrast. measure vg1, vg2 and vg3. g g 1 = 20 log (vg1/0.0357) g g 2 = 20 log (vg2/0.0357) g g 3 = 20 log (vg3/0.0357) (see fig. 5 for definitions of vg1, vg2 and vg3.) input sig8 to (a) and adjust serial bus register bright so that the output at tp44 is 9vp-p (black-black). read the point where the gain of the non-inverted output at tp44 changes when serial bus register g 1 = 0h and 0ffh from the input signal ire level. v g 1mn when g 1 = 0h, and v g 1mx when g 1 = 0ffh. input sig8 to (a) and adjust serial bus register bright so that the output at tp44 is 9vp-p (black-black). read the point where the gain of the non-inverted output at tp44 changes when serial bus register g 2 = 0h and 0ffh from the input signal ire level. v g 2mn when g 2 = 0h, and v g 2mx when g 2 = 0ffh. difference in black level potential between rgb output signals g gain g 1 adjustment variable range g 2 adjustment variable range g g 1 g g 2 g g 3 23.0 26.0 29.0 db 12.0 15.0 18.0 db 18.0 21.0 25.0 db v g 1mn v g 1mx v g 2mn v g 2mx 0 ire 100 ire 100 ire 0 ire input sig4 to (a) and adjust serial bus register psig-brt so that the output at tp39 is 9vp-p (black-black). measure the time it takes to change to an amplitude of 9vp-p. tpsigh: rising edge, tpsigl: falling edge psig transition time t psigh t psigl 1.5 3.0 s 1.5 3.0 s input sig5 (vl = 350mv) to (a) and measure the voltage (white- white) at which the white limiter activates for inverted output and non-inverted output at tp41, tp44 and tp46, respectively. rgb output white limiter operation voltage vwlim 1.3 1.5 1.7 v input sig5 (vl = 0mv) to (a) and adjust v54 so that the output at tp44 is 9vp-p (black-black). measure the dc voltage at tp41, tp44 and tp46 and obtain the difference versus the rgb output voltage vout. black limiter dc voltage difference ? vblim 0 100 mv item symbol conditions min. typ. max. unit
? 18 CXA2543R tdsyl tdsyh hplln hpllp 430 630 830 ns 4.7 5.0 5.3 s 500 hz 500 hz ntsc pal 0 100 mv atbpf atrapn atrapp demlpf wssep vssep ?6 ?0 db ?6 ?0 db ? ? db ? ? db ?0 ?0 db ?0 ?0 db 0.8 1.0 1.3 mhz 2.0 s 40 60 mv ntsc 1.5mhz pal 2.0mhz ntsc 5.5mhz pal 6.8mhz ntsc pal amount of bpf attenuation amount of trap attenuation r-y, b-y and lpf characteristics input sync signal width sensitivity sync separation input sensitivity sync separation output delay time horizontal pull-in range sync separation, tg block filter characteristics assume the chroma amplitude at tp53 when sig5 (vl = 0mv) is input to (a) and sig1 (0db at input center frequency (3.58hz or 4.43hz)) is input to (b) as 0db. obtain the amount by which the output at tp53 is attenuated when the frequencies noted on the right are input. sw59 = a input sig2 (0db, 3.58hz and 4.43hz) to (a) and measure the output at tp44. assume the amplitude at tp44 during y/c input mode as 0db, and obtain the amount of attenuation during comp input mode. assume the amplitude of the 100khz component of the output at tp44 when sig5 (vl = 150mv) is input to (a) and sig1 (0db, 3.58hz + 100khz) is input to (b) as 0db. obtain the frequency which attenuates the beat component of the output by 3db when the sig1 frequency is increased with respect to 3.58mhz. sw59 = a input sig5 (vl = 0mv, vs = 143mv, ws variable) to (a) and confirm that it is synchronized with the hd output at tp23. gradually narrow the ws of sig5 from 4.7 s and obtain the ws at which synchronization with the hd output at tp23 is lost. input sig5 (vl = 0mv, ws = 4.7 s, vs = variable) to (a) and confirm that it is synchronized with the hd output at tp23. gradually reduce the vs of sig5 from 143mv and obtain the vs at which synchronization with the hd output at tp23 is lost. input sig5 (vl = 0mv, ws = 4.7 s, vs = 143mv) to (a) and measure the delay time with the rpd output at tp12. tdsyl is from the falling edge of the input hsync to the falling edge of the rpd output at tp12, and tdsyh is from the falling edge of the input hsync to the rising edge of the rpd output at tp12. input sig5 (vl = 0mv, ws = 4.7 s, vs = 143mv, horizontal frequency variable) to (a) and confirm that it is synchronized with the hd output at tp23. obtain the frequency f h at which the input and output are synchronized by changing the horizontal frequency of sig5 from the non-synchronized condition. hplln = f h ?15734 hpllp = f h ?15625 ? vwlim white limiter dc voltage difference input sig5 (vl = 350mv) to (a). measure the dc voltage at tp41, tp44 and tp46 and obtain the difference versus the rgb output voltage vout. 3.0 v vdroff rgb output range when frp polarity reverse is stopped input sig8 to (a). assume the black limiter level of the output at tp41, tp44 and tp46 when serial bus register bright = 0h as vdrb and the white limiter level when bright = offh as vdrw. vdroff = vdrw ?vdrb item symbol conditions min. typ. max. unit
? 19 CXA2543R ttlh tthl ? t dtyhc vtextb vtextw tdexth tdextl extbk extwt 30 ns 30 ns 10 ns 47 50 53 % 0.8 1.0 1.2 v 1.8 2.0 2.2 v 50 100 150 ns 50 100 150 ns 0 v 3.5 v 180 ns output transition time (p12 * 3 pin) cross-point time difference hck duty input sig5 (vl = 0mv) to (a). measure the transition time for each output. load = 30pf (see fig. 3.) input sig5 (vl = 0mv) to (a). measure hck1/hck2. load = 30pf (see fig. 4.) input sig5 (vl = 0mv) to (a). measure the hck1/hck2 duty. load = 30pf load setup time, activated by the rising edge of sclk. (see fig. 6.) data setup time, activated by the rising edge of sclk. (see fig. 6.) load hold time, activated by the rising edge of sclk. (see fig. 6.) data hold time, activated by the rising edge of sclk. (see fig. 6.) sclk pulse width. (see fig. 6.) sclk pulse width. (see fig. 6.) load pulse width. (see fig. 6.) 150 150 150 150 1 160 160 ns ns ns ns ns ns s ts0 ts1 th0 th1 tw1l tw1h tw2 serial transfer block data setup time data hold time minimum pulse width input sig5 (vl = 0mv) to (a) and sig6 (vl variable) to (c). raise the sig6 amplitude (vl) from 0v and assume the voltage where the outputs at tp41, tp44 and tp46 go to black level as vtextb. then raise the amplitude further and assume the voltage where these outputs go to white level as vtextw. sw6, sw7, sw8 = b input sig5 (vl = 0mv) to (a) and sig6 (vl = 3v) to (c). measure the rise delay time td1ext and the fall delay time td2ext of the outputs at tp41, tp44 and tp46. (see fig. 2.) sw6, sw7, sw8 = b input sig5 (vl = 0mv) to (a) and sig6 (vl = 1.7v) to (c). measure the difference from the black level of the outputs at tp41, tp44 and tp46. sw6, sw7, sw8 = b input sig5 (vl = 0mv) to (a) and sig6 (vl = 2.7v) to (c). measure the difference from the black level of the outputs at tp41, tp44 and tp46. sw6, sw7, sw8 = b textmin input sig5 (vl = 0mv) to (a) and sig6 (vl = 2.7v) to (c). measure the minimum pulse width at which each of the outputs at tp41, tp44 and tp46 reach the white limiter. sw6, sw7, sw8 = b external i/o characteristics external rgb input threshold voltage propagation delay time between external rgb input and output output blanking level during external rgb input output white level during external rgb input minimum pulse width during external rgb input item symbol conditions min. typ. max. unit
? 20 CXA2543R setting 2 power supply characteristics digital block i/o characteristics description of electrical characteristics measurement methods serial bus register initial values item symbol serial bus mode settings input system aspect s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings low level input voltage high level input voltage input current cki pin low input current cki pin high input current high level output voltage low level output voltage high level output voltage low level output voltage high level output voltage low level output voltage output off leak current i cc 11 i cc 12 i cc 13 i cc 2a i cc 2b i dd 1 i dd 2 vil vih ii1 ii2 ii3 voh1 vol1 voh2 vol2 voh3 vol3 ioff comp comp y/c y/color difference comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc ntsc panel lcx018 4:3 16:9 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 shs1 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h psig-brt 80h 80h 80h 80h 80h 78h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h (? don't care, adj: adjustment, set: setting) horizontal afc adjustment current consumption v cc 1 current consumption v cc 2,3 current consumption v dd
? 21 CXA2543R y signal block item symbol serial bus mode settings input system aspect s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings video maximum gain contrast characteristics typ contrast characteristics min y signal frequency response 1 y signal frequency response 2 picture quality adjustment variable amount 1 picture quality adjustment variable amount 2 carrier leak y signal i/o delay time gv gcnttp gcntmn fcyyc fcycmn fcycmp fcl gshp1x gshp1n gshp2x gshp2n crleky tdyyc tdycmn tdycmp comp comp comp y/c comp comp y/c y/c y/c comp comp comp y/c comp comp ntsc ntsc ntsc ntsc ntsc pal ntsc ntsc ntsc ntsc ntsc ntsc pal panel through through through through through through through through through through through through through through through 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0a0h 0a0h 0a0h 0a0h 0a0h 0a0h 0a0h 60h 60h 60h 60h 60h 96h 96h 96h 0ffh 80h 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h psig-brt 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h (? don't care, adj: adjustment, set: setting)
? 22 CXA2543R chroma signal block item symbol serial bus mode settings input system aspect s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings acc amplitude characteristics 1 acc amplitude characteristics 2 apc pull-in range color adjustment characteristics max color adjustment characteristics min hue adjustment range max hue adjustment range min killer operation input level demodulation output amplitude ratio ntsc demodulation output phase difference ntsc demodulation output amplitude ratio pal demodulation output phase difference pal acc1 acc1 acc2 acc2 fapcn fapcp gcolmx gcolmn huemx huemn ackn ackp vrbn vgbn q rbn q gbn vrbp vgbp q rbp q gbp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp comp ntsc pal ntsc pal ntsc pal ntsc ntsc ntsc ntsc ntsc pal ntsc ntsc ntsc ntsc pal pal pal pal panel through through through through through through through through through through through through through through through through through through through through 80h 80h 80h 80h 80h 80h 80h 80h 0ffh 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0ffh 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 96h 96h 96h 96h 96h 96h 96h 96h 96h 96h 60h 60h 60h 60h 60h 60h 60h 60h 60h 60h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h psig-brt 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h (? don't care, adj: adjustment, set: setting)
? 23 CXA2543R chroma signal block rgb signal output block item symbol serial bus mode settings input system aspect s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings color difference input color adjustment characteristics max color difference input color adjustment characteristics min color difference balance color difference input balance adjustment r color difference input balance adjustment b g-y matrix characteristics ntsc g-y matrix characteristics pal rgb signal and psig output dc voltage rgb signal and psig output dc voltage difference rgb and psig output limiter operation voltage amount of change in brightness amount of change in psig gexcmx gexcmn vexcbl gexrmx gexrmn gexbmx gexbmn vexgbn vexgrn vexgbp vexgrp vout ? vout vlimmx vlimmn brtmx brtmn psigmx psigmn y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference y/color difference ntsc ntsc pal pal panel through through through through through through through through through through through through through through through through through through through 80h 80h 80h 0ffh 0h 0ffh 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0ffh 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 96h 96h 96h 96h 96h 96h 96h 96h 96h 96h 96h adj adj 0h 0h 0h 0ffh 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h psig-brt 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 64h 64h 0ffh 0ffh 0ffh 0ffh 0ffh 0h (? don't care, adj: adjustment, set: setting)
? 24 CXA2543R rgb signal output block item symbol serial bus mode settings input system aspect s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings amount of change in sub-brightness difference in gain between rgb output signals difference in rgb output inverted/non-inverted gain difference in black level potential between rgb output signals g gain g 1 adjustment variable range g 2 adjustment variable range psig transition time rgb output white limiter operation voltage black limiter dc voltage difference white limiter dc voltage difference rgb output range when frp polarity reverse is stopped sbbrt ? grgb ? ginv ? vbl g g 1 g g 2 g g 3 v g 1mn v g 1mx v g 2mn v g 2mx t psigh t psigl vwlim ? vblim ? vwlim vdroff panel through through through through through through through through through through through through through through through through through 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0b4h 80h 80h 80h adj adj adj adj adj adj adj 60h 60h 0b4h 0h 0b4h set 80h 80h 80h 80h adj adj adj 46h 46h 46h 46h 80h 80h 0ffh 80h 0ffh 80h set 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h set 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 78h 78h 78h 0h 0ffh 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0d7h 0d7h 0d7h 0h 0h 0h 0ffh 0h 0h 0h 0h 0h 0h psig-brt 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0ffh 0ffh 80h 80h 80h 80h (? don't care, adj: adjustment, set: setting)
? 25 CXA2543R sync separation, tg block filter characteristics external i/o characteristics item symbol serial bus mode settings input system panel s/h hue color bright contrast r-brt b-brt g 1 g 2 dac settings psig-brt (? don't care, adj: adjustment, set: setting) amount of bpf attenuation amount of trap attenuation r-y, b-y and lpf characteristics input sync signal width sensitivity sync separation input sensitivity sync separation output delay time horizontal pull-in range output transition time cross-point time difference hck duty external rgb input threshold voltage propagation delay time between external rgb input and output output blanking level during external rgb input output white level during external rgb input minimum pulse width during external rgb input atbpf comp set set y/c comp comp comp comp comp comp ntsc pal ntsc ntsc pal through 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 60h 60h 60h 60h 60h 60h 60h 60h 60h 60h 80h 80h 80h 80h 80h 80h 80h 80h 80h 64h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 0h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h through through through through through through through through through through through through through through through through through through through through atrapn atrapp demlpf wssep vssep tdsyl tdsyh hplln hpllp ttlh tthl ? t dtyhc vtextb vtextw tdexth tdextl extbk extwt textmin aspect
? 26 CXA2543R s i g 6 t p 4 1 , 4 4 , 4 6 n o n - i n v e r t e d o u t p u t t d e x t h t d e x t l 3 v 0 v 5 0 % fig. 2. conditions for measuring the delay between external rgb input and output t t l h 9 0 % t t h l 1 0 % 5 0 % d t d t fig. 3. output transition time measurement conditions fig. 4. cross-point time difference measurement conditions v g 1 n o n - i n v e r t e d o u t p u t v g 2 v g 3 3 . 5 v w h i t e b l a c k 1 . 5 v i n p u t fig. 5. g characteristics measurement conditions
? 27 CXA2543R d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 1 5 t s 1 t h 1 t w 1 h t w 1 l 5 0 % d a t a s c l k 5 0 % t h 0 t w 2 t s 0 l o a d fig. 6. serial transfer block measurement conditions
? 28 CXA2543R input waveforms sg no. waveform sig1 1 4 3 m v 1 5 0 m v 1 5 0 m v s i n e w a v e v i d e o s i g n a l : w i t h / w i t h o u t b u r s t a m p l i t u d e a n d f r e q u e n c y v a r i a b l e ? v a l u e n o t e d o n l e f t : 0 d b sig2 sig3 1 4 3 m v 1 5 0 m v ? v a l u e n o t e d o n l e f t : 0 d b c h r o m a s i g n a l : b u r s t , c h r o m a f r e q u e n c y ( 3 . 5 7 9 5 4 5 m h z , 4 . 4 3 3 6 1 9 m h z ) c h r o m a p h a s e a n d b u r s t f r e q u e n c y v a r i a b l e 1 4 3 m v 3 5 7 m v r a m p w a v e f o r m 1 h sig4 sig5 1 4 3 m v 1 5 0 m v 5 - s t e p s t a i r c a s e w a v e f o r m 1 h v l v s w s v l a m p l i t u d e v a r i a b l e v s v a r i a b l e : 1 4 3 m v u n l e s s o t h e r w i s e s p e c i f i e d w s v a r i a b l e : 4 . 7 s u n l e s s o t h e r w i s e s p e c i f i e d f h v a r i a b l e : 1 5 . 7 3 4 k h z ( n t s c ) o r 1 5 . 6 2 5 k h z ( p a l ) u n l e s s o t h e r w i s e s p e c i f i e d f h
? 29 CXA2543R sg no. waveform sig6 v l v l a m p l i t u d e v a r i a b l e h o r i z o n t a l s y n c s i g n a l 3 0 s 5 s sig7 1 4 3 m v 7 5 m v f r e q u e n c y v a r i a b l e 1 7 5 m v sig8 1 4 3 m v 3 5 7 m v 1 0 - s t e p s t a i r c a s e w a v e f o r m 1 h sig9 v l v s w s v l a m p l i t u d e v a r i a b l e v s v a r i a b l e : 1 4 3 m v u n l e s s o t h e r w i s e s p e c i f i e d w s v a r i a b l e : 4 . 7 s u n l e s s o t h e r w i s e s p e c i f i e d f h v a r i a b l e : 1 5 . 7 3 4 k h z ( n t s c ) o r 1 5 . 6 2 5 k h z ( p a l ) u n l e s s o t h e r w i s e s p e c i f i e d f h 2 t p u l s e w a v e f o r m
? 30 CXA2543R electrical characteristics measurement circuit v 6 2 t p 1 1 t p 1 7 0 . 4 7 0 . 4 7 4 7 0 . 1 i c c 2 0 . 4 7 t p 4 4 3 0 0 p t p 4 6 3 0 0 p t p 3 9 1 0 0 0 0 p 0 . 0 1 a b 0 . 0 1 a b t p 5 3 ( e ) ( d ) 0 . 0 6 8 1 5 k 0 . 2 2 s w 5 4 v 5 4 * 1 * 2 1 4 7 0 . 1 + 4 . 5 v i c c 1 a b ( b ) 1 5 k * 6 s w 6 4 v 6 4 * 4 4 7 0 . 1 3 v i c c 3 c t p 1 2 1 k 3 3 k 2 2 0 p 0 . 0 1 3 . 3 1 0 k 6 8 0 0 p * 3 0 . 4 7 7 5 0 0 . 0 3 3 ( c ) a b a b a b * 5 ( a ) t p 1 8 t p 1 9 t p 2 0 t p 2 1 t p 2 2 t p 2 3 t p 2 4 t p 2 5 t p 2 6 t p 2 7 t p 2 8 t p 2 9 t p 3 0 t p 3 2 t p 3 3 t p 3 4 t p 3 5 t p 3 6 + 1 2 v t p 4 1 3 0 0 p v c c 1 b - y i n r - y i n c o u t b l k l i m a p c v x o o u t v x o i n v r e g c i n t e s t 3 y i n p i c f 0 a d j p w r s t v d v s s 2 e n x e n v c k 1 v c k 2 v s t x v s t f l d i n h d p c g x p c g h c k 1 h c k 2 h s t x h s t v d d 1 c k o c k i v s s 1 r p d t e s t 2 e x t b e x t g e x t r s . s e p i n h . f i l o u t s y n c i n g n d 1 t r a p s c l k d a t a l o a d r g t f b p s i g g n d 3 p s i g v c c 3 b o u t f b b g o u t f b g r o u t f b r v c c 2 s i g . c e n t e r 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 4 6 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 s w 5 2 s w 5 1 s w 5 9 v d i n t e s t 1 g n d 2 0 . 4 7 1 0 k s w 6 s w 7 s w 8 t p 1 0 t p 9 t p 6 0 4 5 0 . 0 1 0 . 0 1 v 1 4 s w 6 2 l * 1 used crystal: kinseki cx-5f frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pf ntsc: 3.579545mhz pal: 4.433619mhz * 2 ntsc: shorted, pal: 18pf * 3 variable capcitance diode: 1t369 (sony) * 4 dcx501 mode: l value: 4.7 h, c value: 22pf lcx018 (4:3) mode: l value: 4.7 h, c value: 22pf lcx018 (16:9) mode: l value: 2.2 h, c value: 33pf * 5 trap (tdk) ntsc: nlt4532-s3r6b pal: nlt4532-s4r4 * 6 resistance value tolerance: 2%, temperature coefficient: 200ppm or less
? 31 CXA2543R description of operation the CXA2543R incorporates the three functions of an rgb decoder block, an rgb driver block and a timing generator (tg) block onto a single chip using bi-cmos technology. 1) rgb decoder block input mode switching the input mode can be switched between composite input, y/c input and y/color difference input by the serial bus settings. during composite input: the composite signal is input to pins 3, 59 and 61. during y/c input: the y signal is input to pins 3 and 61, and the c signal to pin 59. during y/color difference input: the y signal is input to pins 3 and 61, the b-y signal to pin 51, and the r-y signal to pin 52. system switching the input system can be switched between ntsc and pal (dpal using external delay lines and spal ) by the serial bus settings. trap, bpf the center frequency of the built-in trap and bpf can be switched to 3.58hz during ntsc and 4.43hz during pal. during composite input, the y signal enters the trap circuit and the c signal enters the bpf. these signals do not pass through the trap or bpf during y/c input and y/color difference input. acc detection, acc amplifier the amplitude of the burst signal output from the acc amplifier is detected and the acc amplifier is controlled to maintain the burst signal amplitude at a constant level. vxo, apc detection the vxo local oscillation circuit is a crystal oscillation circuit. the phases of the input burst signal and the vxo oscillator output are compared in the apc detection block, and the detective output is used to form a pll loop that controls the vxo oscillation frequency, which means that the need for adjustments is eliminated. external inputs these are digital inputs with two thresholds. when one of the rgb inputs is higher than the lower threshold vth1 ( 1.0v), all rgb outputs go to black level. when the higher threshold vth2 ( 2.0v) is exceeded, the output for only the signal in question goes to white level, while the other outputs remain at black level.
? 32 CXA2543R sample-and-hold circuit as lcd panels sample rgb signals simultaneously, rgb signals output from the CXA2543R must be sampled-and-hold in sync with the lcd panel drive pulses. s / h 4 s / h 4 s / h 4 g r b s / h 2 s h 2 s / h 1 s h 1 s / h 3 s h 3 s h 4 h c k 1 a b c 2) rgb driver block g correction in order to support the characteristics of lcd panels, the i/o characteristics are as shown in fig. 1. the characteristics change as shown in fig. 2 by adjusting the serial bus register g 1, and as shown in fig. 3 by adjusting g 2. i n p u t o u t p u t f i g . 1 a b i n p u t o u t p u t f i g . 2 a b i n p u t o u t p u t f i g . 3 a ' b ' a b b ' the sample-and-hold circuit performs sample-and-hold by receiving the sh1 to sh4 pulses from the tg block. since lcd panels perform color coding using an rgb delta arrangement, each horizontal line must be compensated by 1.5 dots. this relationship is reversed during right/left inversion. this compensation timing is also generated by the tg block. the sample-and-hold timing changes according to the phase relationship with the hck1 pulse, so the timing should be set to shs1, 2 or 3 in accordance with the actual board. rgt = h (normal) rgt = l (inverted) shs1 sh1 sh2 sh3 sh4 a b through c c a through b b c through a shs2 shs3 shs1 sh1 sh2 sh3 sh4 through b a c through a c b through c b a shs2 shs3 lcx018 rgt = h (normal) rgt = l (inverted) shs1 sh1 sh2 sh3 sh4 b through a c a through c b c through b a shs2 shs3 shs1 sh1 sh2 sh3 sh4 b a through c a c through b c b through a shs2 shs3 sh1: r signal sh pulse sh2: g signal sh pulse sh3: b signal sh pulse sh4: rgb signal sh pulse dcx501
? 33 CXA2543R rgb output rgb outputs (pins 41, 44, and 46) are inverted each horizontal line by the frp pulse supplied from the tg block as shown in the figure below. feedback is applied so that the center voltage (vsig center) of the output signal matches the reference voltage (v cc 2 + gnd2)/2 (or the voltage input to sig center (pin 50)). in addition, the white level output is clipped by the vsig center 0.7v, and the black level output is clipped by the limiter operation point that is adjusted at the blklim (pin 54). v i d e o i n f r p r g b o u t b l a c k l e v e l l i m i t e r w h i t e l e v e l l i m i t e r w h i t e l e v e l l i m i t e r b l a c k l e v e l l i m i t e r v s i g c e n t e r 3) tg block pll and afc circuits the tg block contains a pll circuit phase comparator and frequency division counter, and a pll circuit can be comprised by connecting an external vco circuit. the pll error detection signal is generated at the following timing. the phase comparison output of the entire bottom of hsync and the internal frequency division counter becomes rpd. rpd output is converted to dc error with the lag-lead filter, and then it changes the capacitance of variable capacitance diode to stabilize the oscillation frequency at 1066f h in the dcx501bk and lcx018ak (4:3) mode, 1417f h in the lcx018ak (16:9) mode. the pll of this system is adjusted by setting the the reverse bias voltage of the varicap diode (v14) so that the point at which rpd changes is at the center of the window depicted in the figure below. w s w h w l h s y n c r p d w l = w h h position the horizontal display position can be set at 2f h intervals in 32 different ways by the serial bus settings. the picture center is set at the internal default value, but because there is a difference between the rgb signal and the drive pulse delays on the actual board, the picture center may not match the design center. in this case, adjust with the serial bus.
? 34 CXA2543R right/left inversion the lcd panel is arranged in a delta arrangement, where identical signal lines are offset by 1.5 dots from adjoining lines. for this reason, a 1.5-bit offset is attached to the horizontal start pulse (hst) between odd lines and even lines. hck and s/h are also 1.5-bit offset. when the panel is driven by left scan (reverse scan), this offset relationship is inverted for even and odd lines. moreover, since the dot arrangement is asymmetrical, the hst position is also changed. rgt = h: right scan mode rgt = l: left scan mode h s c a n n e r l e f t s c a n ( r e v e r s e s c a n ) r i g h t s c a n ( n o r m a l s c a n ) d i s p l a y a r e a v s c a n n e r l c d p a n e l wide mode (dcx501bk mode) setting the wide mode by switching the aspect with the serial bus shifts the unit to wide mode. in the dcx501bk mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-wide display. during wide mode, vertical pulse eliminator scanning of 1/4 for ntsc or 1/2 and 1/4 for pal are performed, and the video signal is compressed to achieve a 16:9 aspect ratio. in addition, in areas outside the display area, black is displayed in the 28 lines, respectively at the top and bottom of this display area by performing high-speed scanning the method of black display is a writing method by psig. by setting psig level during high-speed scanning to black display level and writing this black display level at the pcg timing, reliable black display is realized within the limited v blanking period. during this period, hst is masked and video signal input is limited. see the attached sheets for detailed timing. d i s p l a y a r e a d i s p l a y a r e a b l a c k d i s p l a y a r e a b l a c k d i s p l a y a r e a v e r t i c a l h i g h - s p e e d s c a n n i n g v e r t i c a l p u l s e e l i m i n a t o r s c a n n i n g 1 6 : 9 d i s p l a y 4 : 3 d i s p l a y 2 2 5 l i n e s 1 6 9 l i n e s 2 8 l i n e s 2 8 l i n e s d c x 5 0 1 b k
? 35 CXA2543R ac driving of lcd panels during no signal hst, xhst, hck1, hck2, vst, xvst, vck1, vck2, pcg, xpcg, en, xen, hd, vd, and frp are made to run freely so that the lcd panel is ac driven even when there is no composite sync from the sync in pin. during this time, the hsync separation circuit stops and the pll counter is made to run freely. in addition, the vsync separation circuit is also stopped, so the auxiliary v counter is used to create the reference pulse for generating vd, vst and xvst. the cycle of this v counter is designed to be 525/2h for ntsc and 625/2h for pal. however, when there is no vertical sync signal for 5 fields, the no signal state is assumed and the free running vd, vst and xvst pulses are generated from the next field. in addition, rpd is kept at high impedance when there is no signal in order to prevent the afc circuit from causing errors due to phase comparison. d u r i n g h i g h - s p e e d s c a n n i n g d u r i n g n o r m a l - s p e e d s c a n n i n g d o u b l e - s p e e d s c a n n i n g s t o p 1 h c y c l e h s t v c k n f r p ( i n t e r n a l p u l s e ) p c g
? 36 CXA2543R description of serial control operation 1) control method control data consists of 16 bits of data which is loaded one bit at a time at the rising edge of sclk. this loading operation starts from the falling edge of load and is completed at the next rising edge. (d13 to d15 are dummy data.) digital block control data is established by the vertical sync signal and the load "h". if data is transferred multiple times for the same item, the data immediately before the vertical sync signal is valid. analog (electronic attenuator) block control data becomes valid each time the load signal is input. d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d a t a s c l k l o a d serial transfer timing 2) serial data map the serial data map is as follows. d15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pcg width en width pcg position en position 0 0 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 s/h phase hd-position h-position hue color bright contrast r-brt b-brt g 1 g 2 psig-brt vd polarity hd polarity supported panel external v sync frp polarity sync gen frp256 inversion mode 0 0 pal decima -tion aspect up/down inversion y/color difference clamp field determi -nation system input switching note) any data transfer performed when addresses d8, d9, d10, d11, d12 = 1, 1, 1, 1, 1 (shadowed portion) will result in test mode regardless of other data settings. do not transfer data with these addresses set this way. * * * 1 1 1 1 1 test
? 37 CXA2543R 3) serial data mode settings (x: don't care) input switching d1 d0 0 x composite input (default) 1 0 y/c input 1 1 y/color difference input system switching d3 d2 0 x ntsc (default) 1 0 d-pal 1 1 s-pal supported panel switching d4 0 dcx501bk (default) 1 lcx018ak aspect switching d5 0 4:3 (default) 1 16:9 sample-and-hold timing switching d7 d6 0 0 shs1 (default) 0 1 shs2 1 0 shs3 1 1 through (sample-and-hold not performed) hd output polarity switching d0 0 negative polarity (default) 1 positive polarity vd output polarity switching d1 0 negative polarity (default) 1 positive polarity y/color difference clamp position switching this switches the position at which the r-y and b-y input signals are clamped during y/color difference input mode. d2 0 pedestal position (default) 1 sync position mode switching this is the test mode. set to normal mode. d3 0 normal mode (default) 1 test mode
? 38 CXA2543R sync generator function this stops outputs other than vd and hd of the tg block. d4 0 off (default) 1 on note) make sure that vcc2, 3 (12v) and lcd panel power supply should be turned off during sync generator on. up/down inversion function this switches the up/down inverted display. d5 0 down (normal display) (default) 1 up (up/down inverted display) frp256 field inversion this further inverts the polarity of the rgb output that is inverted every 1h for 256 fields. d6 0 off (default) 1 on frp polarity inversion function d7 0 on (1h inversion) (default) 1 off (polarity not inverted) external field identification input switching internal field identification is not performed and an externally field input source is used. d0 0 off (internal identification) (default) 1 on (external input) external vsync input switching internal vsync separation is not performed and an externally input vsync is used. d1 0 off (internal separation) (default) 1 on (external input) pal pulse elimination switching this switches on/off the pal pulse elimination function during pal mode. d2 0 on (elimination performed) (default) 1 off (elimination not performed)
? 39 CXA2543R h position setting d4 d3 d2 d1 d0 0 0 0 0 0 : : : : : 1 0 0 0 0 (default) : : : : : 1 1 1 1 1 variable in 2f h (= 1 bit) increments 1 s t e p 1 s t e p c l k ( i n t e r n a l ) h s t 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 hd phase setting d4 d3 d2 d1 d0 0 0 0 0 0 (default) : : : : : 1 1 1 1 1 variable in 4f h (= 1 bit) increments 3 1 s t e p s h d 0 0 0 0 0 1 1 1 1 1 h s y n c
? 40 CXA2543R pcg pulse position this sets the pcg pulse position (a in the figure below). d1 d0 0 0 (default) 1 1 dcx501 and lcx018 (4:3) mode: variable in 6f h (= 1 bit) increments lcx018 (16:9) mode: variable in 9f h (= 1 bit) increments pcg pulse width this sets the pcg pulse width (b in the figure below). d5 d4 0 0 (default) 1 1 dcx501 and lcx018 (4:3) mode: variable in 8f h (= 1 bit) increments lcx018 (16:9) mode: variable in 12f h (= 1 bit) increments en pulse position this sets the en pulse position (c in the figure below). d1 d0 0 0 (default) 1 1 dcx501 and lcx018 (4:3) mode: variable in 4f h (= 1 bit) increments lcx018 (16:9) mode: variable in 6f h (= 1 bit) increments en pulse width this sets the en pulse width (d in the figure below). d5 d4 0 0 (default) 1 1 dcx501 and lcx018 (4:3) mode: variable in 8f h (= 1 bit) increments lcx018 (16:9) mode: variable in 12f h (= 1 bit) increments h s y n c p c g e n b a d c setting correspondence table set the positions and widths for the en and pcg pulses as follows when driving the dcx501bk and the lcx018ak. lcx018ak width pcg pulse en pulse d5 1 0 d4 0 0 d1 0 1 position d0 0 1 dcx501bk width pcg pulse en pulse d5 0 0 d4 0 0 d1 0 0 position d0 0 0
? 41 CXA2543R 4) serial data electronic attenuator (d/a converter) settings hue d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) color d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) bright d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) contrast d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) r-brt d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) b-brt d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 0 0 0 0 0 (default) g 1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 (default) g 2 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 (default) psig-brt d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 (default) 5) test mode test mode results if data is sent to the following addresses. for this reason, do not perform data transfer using these addresses. d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 * * * * * * * * note) if data transfer is performed in these addresses, the chip will enter test mode regardless of the data set.
? 42 CXA2543R dcx501bk color coding diagram the delta arrangement is used for the color coding in the lcd panels with which this ic is compatible. note that the shaded region within the diagram is not displayed. dcx501bk pixel arrangement a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a 8 0 0 1 2 8 0 3 d u m m y 2 v l i n e 3 v l i n e 2 v l i n e 1 d u m m y 1 h s w 1 h s w 2 6 6 h s w 2 6 7 1 1 2 2 5 2 2 7 g b r g b r g b r g b r g b b r g b r g b r g b r g b r g b r g b r g b r g b r g b b r g b r g b r g b r g b r g b r g b r g b r g b r g b g b r g b r g b r g b r g b b r g b r g b r g b r g b r g b r g b r g b r g b r g b d i s p l a y a r e a h s w 2 v l i n e 2 2 5 v l i n e 2 2 4 h s w 2 6 8 b r g b r g b r g b r g b r g a a a a a a a a a a a a a a a a a a a a a a a a a a a a p r e c h a r g e s w h s w 3 r g b r r g b r b r r g b r r g b r r g b r g b r g b r g b r g b r g r g r r g r g r r g b r g b r g b r g b r g b r g p h o t o - s h i e l d i n g a r e a
? 43 CXA2543R lcx018ak pixel arrangement (4:3) d l 1 d l 2 1 2 3 5 6 3 5 7 d r 1 d r 2 e v e n = 7 d o t s o d d = 7 d o t s 4 4 4 5 4 6 4 7 3 1 1 3 1 2 3 1 3 3 1 4 4 : 3 a r e a s i d e b l a c k s i d e b l a c k g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w 2 2 4 2 2 5 1 2 3 4 2 d o t s 2 2 5 d o t s ( e f f e c t i v e 8 . 7 7 5 m m ) 2 d o t s b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r e v e n = 1 3 3 d o t s o d d = 1 3 2 d o t s e v e n = 7 d o t s o d d = 8 d o t s r e v e n = 1 0 8 3 d o t s o d d = 1 0 8 3 d o t s e v e n = 8 0 3 d o t s o d d = 8 0 4 d o t s ( e f f e c t i v e 1 1 . 6 5 1 m m ) e v e n = 1 3 3 d o t s o d d = 1 3 2 d o t s
? 44 CXA2543R lcx018ak pixel arrangement (16:9) g a t e s w d l 1 g a t e s w d l 2 g a t e s w 1 g a t e s w 2 g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w g a t e s w 3 5 5 g a t e s w g a t e s w 3 5 6 g a t e s w 3 5 7 g a t e s w d r 1 g a t e s w d r 2 e v e n = 7 d o t s o d d = 8 d o t s e v e n = 1 0 8 3 d o t s o d d = 1 0 8 3 d o t s e v e n = 7 d o t s o d d = 7 d o t s 2 2 4 2 2 5 1 2 3 4 2 d o t s 2 2 5 d o t s ( e f f e c t i v e 8 . 7 7 5 m m ) 3 2 d o t s b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r r r r r r r r r r r r r r r r r r r b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b g b r g r r r r r r r r r r r r r r r r r r r e v e n = 1 0 6 9 d o t s o d d = 1 0 6 8 d o t s ( e f f e c t i v e 1 5 . 4 9 3 m m )
? 45 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 3 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 1 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 7 9 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 2 . 0 s ( 3 4 f h ) 1 2 f h 2 0 . 5 f h 7 . 5 s ( 1 2 5 . 5 f h ) 5 . 0 s ( 8 3 . 5 f h ) 1 . 5 s ( 2 5 f h ) e v e n f i e l d o d d f i e l d o d d f i e l d e v e n f i e l d 2 . 5 s ( 4 2 f h ) 6 . 0 s ( 1 0 1 f h ) 1 . 0 s ( 1 7 f h ) 7 6 f h dcx501bk horizontal direction timing chart ntsc/pal unless otherwise specified, serial settings are the default values. rgt: h (normal scan) 1066f h odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 46 CXA2543R 1 2 f h e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 3 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 1 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 7 9 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 2 . 0 s ( 3 4 f h ) 1 2 4 f h 8 2 f h 1 . 5 s ( 2 5 f h ) 1 . 0 s ( 1 7 f h ) 2 . 5 s ( 4 2 f h ) 6 . 0 s ( 1 0 1 f h ) e v e n f i e l d o d d f i e l d o d d f i e l d e v e n f i e l d 1 9 f h 7 6 f h dcx501bk horizontal direction timing chart ntsc/pal unless otherwise specified, serial settings are the default values. rgt: h (normal scan) 1066f h even line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 47 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 3 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 1 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 7 9 f h ) 2 . 0 s ( 3 4 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 2 0 . 5 f h 1 2 f h 7 . 5 s ( 1 2 5 . 5 f h ) 1 . 0 s ( 1 7 f h ) 2 . 5 s ( 4 2 f h ) 6 . 0 s ( 1 0 1 f h ) 1 . 5 s ( 2 5 f h ) e v e n f i e l d o d d f i e l d o d d f i e l d e v e n f i e l d 7 6 f h 5 . 0 s ( 8 3 . 5 f h ) dcx501bk horizontal direction timing chart ntsc/pal unless otherwise specified, serial settings are the default values. rgt: l (reverse scan) 1066f h odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 48 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 3 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 1 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 7 9 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 2 . 0 s ( 3 4 f h ) 1 2 f h 2 2 f h 1 2 7 f h 8 5 f h 1 . 5 s ( 2 5 f h ) 2 . 5 s ( 4 2 f h ) 1 . 0 s ( 1 7 f h ) 6 . 0 s ( 1 0 1 f h ) e v e n f i e l d o d d f i e l d o d d f i e l d e v e n f i e l d 7 6 f h dcx501bk horizontal direction timing chart ntsc/pal unless otherwise specified, serial settings are the default values. rgt: l (reverse scan) 1066f h even line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 49 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 7 9 f h ) 2 . 0 s ( 3 4 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 3 5 . 5 f h 6 f h 7 . 0 s ( 1 1 7 . 5 f h ) 2 . 2 s ( 3 7 f h ) 6 . 0 s ( 1 0 1 f h ) 2 . 5 s ( 4 1 f h ) 1 . 0 s ( 1 7 f h ) 4 . 5 s ( 7 6 f h ) e v e n f i e l d o d d f i e l d e v e n f i e l d o d d f i e l d 4 . 5 s ( 7 5 . 5 f h ) 0 . 5 s ( 8 f h ) lcx018ak horizontal direction timing chart (4:3) ntsc/pal unless otherwise specified, serial settings are the default values. rgt: h (normal scan), pcg width: lh, en position: hh master clock: 16.773mhz (ntsc) / 16.656mhz (pal) pll counter n: 1066f h odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 50 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) 1 1 6 f h 7 4 f h o d d f i e l d e v e n f i e l d o d d f i e l d e v e n f i e l d 4 . 5 s ( 7 6 f h ) 1 . 0 s ( 1 7 f h ) 2 . 5 s ( 4 1 f h ) 6 . 0 s ( 1 0 1 f h ) 2 . 2 s ( 3 7 f h ) 3 4 f h 6 f h 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 4 . 7 s ( 7 9 f h ) 2 . 0 s ( 3 4 f h ) 0 . 5 s ( 8 f h ) lcx018ak horizontal direction timing chart (4:3) ntsc/pal even line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: h (normal scan), pcg width: lh, en position: hh master clock: 16.773mhz (ntsc) / 16.656mhz (pal) pll counter n: 1066f h
? 51 CXA2543R e n ( p a l ) ( b l k ) h d h s t 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) v c k 1 m c k s y n c h c k 1 v c k 2 p c g e n p s i g f r p ( i n t e r n a l p u l s e ) v s t / v d s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) o d d f i e l d 2 . 2 s ( 3 7 f h ) o d d f i e l d e v e n f i e l d e v e n f i e l d 6 f h 3 5 . 5 f h 4 . 5 s ( 7 5 f h ) 2 . 0 s ( 3 4 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 . 5 f h ) 7 . 0 s ( 1 1 7 . 5 f h ) 1 . 0 s ( 1 7 f h ) 4 . 5 s ( 7 6 f h ) 2 . 5 s ( 4 1 f h ) 6 . 0 s ( 1 0 1 f h ) 4 . 7 s ( 7 9 f h ) 0 . 5 s ( 8 f h ) lcx018ak horizontal direction timing chart (4:3) ntsc/pal odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: l (reverse scan), pcg width: lh, en position: hh master clock: 16.773mhz (ntsc) / 16.656mhz (pal) pll counter n: 1066f h
? 52 CXA2543R 4 . 7 s ( 7 9 f h ) 4 . 7 s ( 7 9 f h ) 4 . 5 s ( 7 5 f h ) 2 . 0 s ( 3 4 f h ) o d d f i e l d e v e n f i e l d 6 . 0 s ( 1 0 1 f h ) 1 . 0 s ( 1 7 f h ) o d d f i e l d e v e n f i e l d 2 . 5 s ( 4 1 f h ) 0 . 5 s ( 8 f h ) 4 . 5 s ( 7 6 f h ) m c k s y n c ( b l k ) h d h s t 1 h c k 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) v c k 1 v c k 2 v s t / v d e n ( p a l ) e n p c g p s i g f r p ( i n t e r n a l p u l s e ) 3 7 f h 6 f h 1 1 9 f h 7 7 f h 2 . 2 s ( 3 7 f h ) lcx018ak horizontal direction timing chart (4:3) ntsc/pal even line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: l (reverse scan), pcg width: lh, en position: hh master clock: 16.773mhz (ntsc) / 16.656mhz (pal) pll counter n: 1066f h
? 53 CXA2543R 4 . 7 s ( 1 0 5 f h ) 4 . 7 s ( 1 0 5 f h ) 4 . 5 s ( 1 0 0 f h ) 2 . 0 s ( 4 5 f h ) 6 . 0 s ( 1 3 4 f h ) 4 . 5 s ( 1 0 1 f h ) 2 . 2 s ( 5 1 f h ) 2 . 5 s ( 5 7 f h ) 0 . 5 s ( 1 1 f h ) m c k s y n c ( b l k ) h d h s t 1 h c k 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) v c k 1 v c k 2 v s t / v d e n ( p a l ) e n p c g p s i g f r p ( i n t e r n a l p u l s e ) 4 7 . 5 f h 6 f h 7 . 0 s ( 1 5 6 . 5 f h ) 4 . 5 s ( 1 0 0 . 5 f h ) o d d f i e l d e v e n f i e l d o d d f i e l d e v e n f i e l d 1 . 0 s ( 2 2 f h ) lcx018ak horizontal direction timing chart (16:9) ntsc/pal odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: h (normal scan), pcg width: lh, en position: hh master clock: 22.295mhz (ntsc) / 22.141mhz (pal) pll counter n: 1417f h
? 54 CXA2543R note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. a a a 4 . 7 s ( 1 0 5 f h ) 4 . 7 s ( 1 0 5 f h ) 4 . 5 s ( 1 0 0 f h ) 2 . 0 s ( 4 5 f h ) 2 . 2 s ( 5 1 f h ) 2 . 5 s ( 5 7 f h ) m c k s y n c ( b l k ) h d h s t 1 h c k 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) v c k 1 v c k 2 v s t / v d e n ( p a l ) e n p c g p s i g f r p ( i n t e r n a l p u l s e ) 6 f h 4 6 f h 1 5 5 f h 9 9 f h 4 . 5 s ( 1 0 1 f h ) 6 . 0 s ( 1 3 4 f h ) 0 . 5 s ( 1 1 f h ) o d d f i e l d e v e n f i e l d o d d f i e l d e v e n f i e l d 1 . 0 s ( 2 2 f h ) lcx018ak horizontal direction timing chart (16:9) ntsc/pal even line unless otherwise specified, serial settings are the default values. rgt: h (normal scan), pcg width: lh, en position: hh master clock: 22.295mhz (ntsc) / 22.141mhz (pal) pll counter n: 1417f h
? 55 CXA2543R 2 . 0 s ( 4 5 f h ) 0 . 5 s ( 1 1 f h ) m c k s y n c ( b l k ) h d h s t 1 h c k 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) v c k 1 v c k 2 v s t / v d e n ( p a l ) e n p c g p s i g f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 1 0 5 f h ) a a a a a a 4 . 7 s ( 1 0 5 f h ) a a a 4 . 5 s ( 1 0 0 f h ) 4 7 . 5 f h 6 f h 7 . 0 s ( 1 5 6 . 5 f h ) 4 . 5 s ( 1 0 0 . 5 f h ) 2 . 2 s ( 5 1 f h ) 4 . 5 s ( 1 0 1 f h ) 2 . 5 s ( 5 7 f h ) 6 . 0 s ( 1 3 4 f h ) o d d f i e l d e v e n f i e l d o d d f i e l d e v e n f i e l d 1 . 0 s ( 2 2 f h ) lcx018ak horizontal direction timing chart (16:9) ntsc/pal odd line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: l (reverse scan), pcg width: lh, en position: hh master clock: 22.295mhz (ntsc) / 22.141mhz (pal) pll counter n: 1417f h
? 56 CXA2543R 4 . 7 s ( 1 0 5 f h ) m c k s y n c ( b l k ) h d h s t 1 h c k 1 h c k 2 s h 1 ( i n t e r n a l p u l s e ) s h 2 ( i n t e r n a l p u l s e ) s h 4 ( i n t e r n a l p u l s e ) s h 3 ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) v c k 1 v c k 2 v s t / v d e n ( p a l ) e n p c g p s i g f r p ( i n t e r n a l p u l s e ) 4 . 7 s ( 1 0 5 f h ) 4 . 5 s ( 1 0 0 f h ) 2 . 0 s ( 4 5 f h ) 4 9 f h 6 f h 1 5 8 f h 1 0 2 f h 2 . 2 s ( 5 1 f h ) 4 . 5 s ( 1 0 1 f h ) 2 . 5 s ( 5 7 f h ) 6 . 0 s ( 1 3 4 f h ) 0 . 5 s ( 1 1 f h ) o d d f i e l d e v e n f i e l d o d d f i e l d e v e n f i e l d 1 . 0 s ( 2 2 f h ) lcx018ak horizontal direction timing chart (16:9) ntsc/pal even line note) the third row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. unless otherwise specified, serial settings are the default values. rgt: l (reverse scan), pcg width: lh, en position: hh master clock: 22.295mhz (ntsc) / 22.141mhz (pal) pll counter n: 1417f h
? 57 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) dcx501bk vertical direction output pulse ntsc vertical direction timing chart odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 58 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) dcx501bk vertical direction output pulse ntsc vertical direction timing chart even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 59 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) dcx501bk vertical direction output pulse pal vertical direction timing chart odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 60 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) dcx501bk vertical direction output pulse pal vertical direction timing chart even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 61 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) 1 6 9 - l i n e d i s p l a y a r e a 1 6 9 - l i n e d i s p l a y a r e a dcx501bk vertical direction output pulse ntsc wide vertical direction timing chart odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field. 1/4 pulse eliminator
? 62 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) 1 6 9 - l i n e d i s p l a y a r e a 1 6 9 - l i n e d i s p l a y a r e a dcx501bk vertical direction output pulse ntsc wide vertical direction timing chart even field 1/4 pulse eliminator note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 63 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) 1 6 9 - l i n e d i s p l a y a r e a dcx501bk vertical direction output pulse pal wide vertical direction timing chart odd field 1/2 and 1/4 pulse eliminator note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 64 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) 1 6 9 - l i n e d i s p l a y a r e a dcx501bk vertical direction output pulse pal wide vertical direction timing chart even field 1/2 and 1/4 pulse eliminator note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 65 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse ntsc vertical direction timing chart (down) odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 66 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse ntsc vertical direction timing chart (down) even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 67 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse pal vertical direction timing chart (down) odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 68 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse pal vertical direction timing chart (down) even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 69 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse ntsc vertical direction timing chart (up) odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 70 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse ntsc vertical direction timing chart (up) even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 71 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse pal vertical direction timing chart (up) odd field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 72 CXA2543R x h d x v d c s y n c ( b l k ) v s t v c k 1 h s t p c g e n f l d ( i n t e r n a l p u l s e ) v d v c k 2 s b l k ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) f r p ( i n t e r n a l p u l s e ) ( 1 f i n v e r s i o n ) lcx018ak vertical direction output pulse pal vertical direction timing chart (up) even field note) the fourth row of the timing chart "blk" is a pulse indicated as a reference and is not a pulse output from pins. frp polarity is not specified for each line and field.
? 73 CXA2543R application circuit (ntsc/pal, comp and y/c input) 0 . 4 7 7 5 0 0 . 0 3 3 * 5 0 . 4 7 0 . 4 7 4 7 0 . 1 + 1 2 v + 3 v 0 . 4 7 0 . 4 7 t o l c d p a n e l 1 5 k * 6 + 4 . 5 v 4 7 0 . 1 * 1 * 2 1 + 4 . 5 v * 4 4 7 0 . 1 + 3 v c 1 k 3 3 k 2 2 0 p 3 . 3 1 0 k 6 8 0 0 p * 3 t o l c d p a n e l 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 4 6 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 0 . 0 1 0 . 0 1 0 . 0 6 8 1 5 k 0 . 2 2 + 4 . 5 v 4 7 k 0 . 0 1 y / c c o m p c i n 1 4 7 k 0 . 0 1 0 . 0 1 c o m p / y i n t o s e r i a l c o n t r o l l e r v c c 1 b - y i n r - y i n c o u t b l k l i m a p c v x o o u t v x o i n v r e g c i n t e s t 3 y i n p i c f 0 a d j p w r s t v d v s s 2 e n x e n v c k 1 v c k 2 v s t x v s t f l d i n h d p c g x p c g h c k 1 h c k 2 h s t x h s t v d d 1 c k o c k i v s s 1 r p d t e s t 2 e x t b e x t g e x t r s . s e p i n h . f i l o u t s y n c i n g n d 1 t r a p s c l k d a t a l o a d r g t f b p s i g g n d 3 p s i g v c c 3 b o u t f b b g o u t f b g r o u t f b r v c c 2 s i g . c e n t e r v d i n t e s t 1 g n d 2 1 0 k 0 . 0 1 4 7 k 3 . 3 k 3 . 3 k o u t i n + 1 2 v s a m p l e p s i g b u f f e r c i r c u i t b u f f 0 . 0 1 1 2 v l * 1 used crystal: kinseki cx-5f frequency deviation: within 30ppm, frequency temperature characteristics: within 30ppm, load capacity: 16pf ntsc: 3.579545hz pal: 4.433619hz * 2 ntsc: shorted, pal: 18pf * 3 variable capcitance diode: 1t369 (sony) * 4 dcx501 mode: l value: 4.7 h, c value: 22pf lcx018 (4:3) mode: l value: 4.7 h, c value: 22pf lcx018 (16:9) mode: l value: 2.2 h, c value: 33pf * 5 trap (tdk) ntsc: nlt4532-s3r6b pal: nlt4532-s4r4 * 6 resistance value variation: 2%, temperature coefficient: 200ppm or less connect to +4.5v during y/c input application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 74 CXA2543R application circuit (ntsc/pal, y/color difference input) 0 . 4 7 7 5 0 0 . 0 3 3 0 . 4 7 0 . 4 7 4 7 0 . 1 + 1 2 v + 3 v 0 . 4 7 0 . 4 7 t o l c d p a n e l + 4 . 5 v 4 7 0 . 1 1 + 4 . 5 v 4 7 0 . 1 + 3 v 1 k 3 3 k 2 2 0 p 3 . 3 1 0 k 6 8 0 0 p * 1 t o l c d p a n e l 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 4 6 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 1 4 2 4 3 4 4 4 5 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 3 6 4 6 1 6 2 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 0 . 1 0 . 1 + 4 . 5 v 4 7 k 0 . 0 1 1 4 7 k 0 . 0 1 0 . 0 1 c o m p / y i n t o s e r i a l c o n t r o l l e r v c c 1 b - y i n r - y i n c o u t b l k l i m a p c v x o o u t v x o i n v r e g c i n t e s t 3 y i n p i c f 0 a d j p w r s t v d v s s 2 e n x e n v c k 1 v c k 2 v s t x v s t f l d i n h d p c g x p c g h c k 1 h c k 2 h s t x h s t v d d 1 c k o c k i v s s 1 r p d t e s t 2 e x t b e x t g e x t r s . s e p i n h . f i l o u t s y n c i n g n d 1 t r a p s c l k d a t a l o a d r g t f b p s i g g n d 3 p s i g v c c 3 b o u t f b b g o u t f b g r o u t f b r v c c 2 s i g . c e n t e r v d i n t e s t 1 g n d 2 1 0 k 0 . 0 1 4 7 k 3 . 3 k 3 . 3 k o u t i n + 1 2 v s a m p l e p s i g b u f f e r c i r c u i t b u f f r - y i n b - y i n 0 . 0 1 + 1 2 v + 4 . 5 v c l * 2 * 1 variable capcitance diode: 1t369 (sony) * 2 dcx501 mode: l value: 4.7 h, c value: 22pf lcx018 (4:3) mode: l value: 4.7 h, c value: 22pf lcx018 (16:9) mode: l value: 2.2 h, c value: 33pf application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 75 CXA2543R example of representative characteristics 6 0 4 0 2 0 0 2 0 4 0 6 0 h u e a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e n t p a l h u e a d j u s t m e n t a n g l e [ d e g ] 3 0 2 5 2 0 1 5 1 0 5 1 0 c o l o r a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e g a i n [ d b ] 5 0 0 1 2 3 4 5 6 b r i g h t a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e n o n - i n v e r t e d b l a c k n o n - i n v e r t e d o u t p u t b l a c k l e v e l [ v ] i n v e r t e d o u t p u t b l a c k l e v e l [ v ] 6 7 8 9 1 0 1 1 1 2 i n v e r t e d b l a c k 5 0 5 1 0 1 5 2 0 2 5 c o n t r a s t a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e o u t p u t g a i n [ d b ] 1 . 5 1 . 0 0 . 5 0 0 . 5 1 . 0 1 . 5 s u b - b r i g h t a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e o u t p u t l e v e l w i t h r e s p e c t t o g o u t p u t [ v ] d a c v a l u e 0 2 4 6 8 1 0 p s i g - b r i g h t a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f o u t p u t l e v e l [ v p - p ]
? 76 CXA2543R c o l o r d i f f e r e n c e b a l a n c e a d j u s t m e n t 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e b - y o u t p u t r - y o u t p u t 2 0 1 5 1 0 5 1 0 c o l o r d i f f e r e n c e c o l o r a d j u s t m e n t c h a r a c t e r i s t i c s 0 2 0 4 0 6 0 8 0 0 a 0 0 c 0 0 e 0 0 f f d a c v a l u e g a i n [ d b ] 5 0 5 4 3 2 4 5 g a i n [ d b ] 3 2 1 0 1 s h a r p n e s s c h a r a c t e r i s t i c s ( c o m p , n t s c ) 0 1 2 3 4 5 f r e q u e n c y [ m h z ] 0 v 2 . 2 5 v 3 0 2 5 2 0 1 5 1 0 1 5 g a i n [ d b ] 5 0 5 1 0 4 . 5 v s h a r p n e s s c h a r a c t e r i s t i c s ( c o m p , p a l ) 0 1 2 3 4 5 f r e q u e n c y [ m h z ] 0 v 2 . 2 5 v 3 0 2 5 2 0 1 5 1 0 1 5 g a i n [ d b ] 5 0 5 1 0 4 . 5 v s h a r p n e s s c h a r a c t e r i s t i c s ( y / c ) 0 2 4 6 8 1 0 f r e q u e n c y [ m h z ] 0 v 2 . 2 5 v 2 5 2 0 1 5 1 0 1 5 2 0 g a i n [ d b ] 1 0 5 0 5 4 . 5 v p i n v o l t a g e [ v ] 4 5 6 7 8 1 0 b l a c k l e v e l l i m i t e r a d j u s t m e n t c h a r a c t e r i s t i c s 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 l i m i t e r l e v e l [ v p - p ] 9
? 77 CXA2543R notes on operation the CXA2543R contains digital circuits, so the set board pattern must be designed in consideration of undesired radiation, interference to analog circuits, etc. care should also be taken for the following items when designing the pattern. make the ic power supply and gnd patterns as plain as possible. in particular, gnd and v ss should not be separated and should be connected to the same gnd pattern as close to the pins as possible. connect the by-pass capacitors between the power supplies and gnd as close to the pins as possible. the trap connected to pin 1 should be located as close to the pin as possible. also, don't pass other signal lines close to this pin or the connected trap. the wiring for the crystal and capacitor connected to pins 56 and 57 should be as short as possible in order to prevent floating capacitance. don't pass other signal lines close to these pins in order to prevent interference such as color unevenness. in addition, the apc pull-in characteristics vary significantly according to the characteristics of the used crystal and the wiring pattern, so be sure to thoroughly investigate these items before using the set. the resistor connected to pin 63 should be located as close to the pin as possible. also, take care not to pass other signal lines close to this pin. the composite/y signal and the external r-y and b-y signals are clamped at the inputs using the capacitors connected to the input pins, so these signals should be input at sufficiently low impedance. the c signal is received by the internal capacitor, so this signal should be directly input at low impedance. the smoothing capacitor of the dc level control feedback circuit in the output block should have a leak current with a small absolute value and variance. a thorough study of the external buffer for psig output should be made before deciding on a circuit to ascertain that it sufficiently brings out the characteristics of the lcd panel. if this ic is used in connection with a circuit other than an lcd, it may cause that circuit to malfunction depending on the order power is supplied to the circuits. thoroughly study the consequences of using this ic with other circuits before deciding on its use. since this ic utilizes a c-mos structure, it may latch up due to excessive noise or power surge greater than the maximum rating of the i/o pins, or due to interface with the power supply of another circuit, or due to the order in which power is supplied to circuits. be sure to take measures against the possibility of latch up. do not apply a voltage higher than v dd or lower than v ss to i/o pins. do not use this ic under operating conditions other than those given. absolute maximum rating values should not be exceeded even momentarily. exceeding ratings may damage the device, leading to eventual breakdown. this ic has a mos structure which is easily damaged by static electricity, so thorough measures should be taken to prevent electrostatic discharge.
? 78 CXA2543R package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e 6 4 p i n l q f p ( p l a s t i c ) 1 2 . 0 0 . 2 1 0 . 0 0 . 2 4 8 3 3 1 1 6 4 9 6 4 3 2 1 7 1 . 2 5 0 . 5 + 0 . 0 8 0 . 1 8 0 . 0 3 m 0 . 1 0 . 1 0 . 1 ( 0 . 5 ) 0 . 5 0 . 2 0 t o 1 0 1 . 7 m a x d e t a i l a a 0 . 1 0 . 1 5 0 . 0 5 l q f p - 6 4 p - l 0 6 1 l q f p 0 6 4 - p - 1 0 1 0 - a y 0 . 3 g

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